Optimizing current conveyors by evolutionary algorithms including differential evolution

Author

Guerra-Gómez, I. ; Tlelo-Cuautle, E. ; McConaghy, T. ; Gielen, G.

Author_Institution

Dept. of Electron., INAOE, Tonantzintla, Mexico

fYear

2009

fDate

13-16 Dec. 2009

Firstpage

259

Lastpage

262

Abstract

An optimization system based on two multi-objective evolutionary algorithms NSGA-II and MOEA/D is presented for sizing analog integrated circuits. The proposed system uses HSPICE as circuit evaluator and its usefulness is highlighted by sizing mixed-mode analog circuits composed of unity-gain cells. That way, the circuits are optimized in voltage- and current-mode in three parameters: gain, bandwidth and offset, and by including as constraint that all transistors are in saturation operation. Comparison of performances between NSGA-II and MOEA/D with and without differential evolution (DE) as genetic operator in the optimization of two current conveyors are given by using standard CMOS integrated circuit technology.

Keywords

SPICE; analogue integrated circuits; current conveyors; evolutionary computation; CMOS integrated circuit technology; HSPICE; MOEA/D; NSGA-II; analog integrated circuits; circuit evaluator; complementary metal-oxide-semiconductor; current conveyors; differential evolution; genetic operator; mixed-mode analog circuits; multi-objective evolutionary algorithm; optimization system; unity gain cells; Analog circuits; Analog integrated circuits; Bandwidth; CMOS integrated circuits; CMOS technology; Constraint optimization; Evolutionary computation; Genetics; Integrated circuit technology; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits, and Systems, 2009. ICECS 2009. 16th IEEE International Conference on

Conference_Location

Yasmine Hammamet

Print_ISBN

978-1-4244-5090-9

Electronic_ISBN

978-1-4244-5091-6

Type

conf

DOI

10.1109/ICECS.2009.5410989

Filename

5410989