Title :
Power Optimization Techniques for DDR3 SDRAM
Author :
Panda, P.R. ; Patel, V. ; Shah, P. ; Sharma, N. ; Srinivasan, V. ; Sarma, D.
Author_Institution :
Indian Inst. of Technol. Delhi, New Delhi, India
Abstract :
With memory contributing to a significant fraction of the overall power consumption, several power management techniques targeting the memory sub-system have been proposed by researchers. In this work, we propose two memory power optimization techniques. We first suggest dynamically varying the queue structure in a memory controller, and next propose an adaptive threshold technique for switching to low power SELF-REFRESH operating mode of the DDR3 SDRAM. With the proposed queue-resizing optimization, the power consumption reduces by up to 93%, while the adaptive threshold technique results in an additional 21% power savings, on an average, over a constant threshold implementation.
Keywords :
DRAM chips; low-power electronics; optimisation; queueing theory; DDR3 SDRAM; adaptive threshold technique; low power SELF-REFRESH operating mode; memory controller; memory power optimization technique; power consumption; power management technique; queue-resizing optimization; Benchmark testing; Memory management; Optimization; Power demand; SDRAM; Switches;
Conference_Titel :
VLSI Design (VLSID), 2015 28th International Conference on
Conference_Location :
Bangalore
DOI :
10.1109/VLSID.2015.59