DocumentCode
3437642
Title
Testing of VLSI regular arrays
Author
Marnane, W.P. ; Moore, W.R.
Author_Institution
Dept. of Eng. Sci., Oxford Univ., UK
fYear
1988
fDate
3-5 Oct 1988
Firstpage
145
Lastpage
148
Abstract
The authors present a unifying approach to testing fine-grained VLSI arrays. The approach covers a wide range of regular arrays and leads directly to test pattern generation. This method can meet the requirements of any single-cell fault model and can cope with restricted access to the boundary of the array. It is shown how existing concepts such as C-testability can be utilized in generating test patterns
Keywords
VLSI; integrated circuit testing; logic testing; VLSI regular arrays testing; single-cell fault model; test pattern generation; unifying approach; Circuit faults; Circuit testing; Controllability; Integrated circuit interconnections; Semiconductor device modeling; Sequential analysis; Signal design; Switches; Test pattern generators; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 1988. ICCD '88., Proceedings of the 1988 IEEE International Conference on
Conference_Location
Rye Brook, NY
Print_ISBN
0-8186-0872-2
Type
conf
DOI
10.1109/ICCD.1988.25679
Filename
25679
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