Evaluation of the positive biased temperature stress stability in HfSiON gate dielectrics

Author

Shanware, A. ; Visokay, M.R. ; Chambers, J.J. ; Rotondaro, A.L.P. ; Bu, H. ; Bevan, M.J. ; Khamankar, R. ; Aur, S. ; Nicollian, P.E. ; McPherson, J. ; Colombo, Luigi

Author_Institution

Silicon Technol. Dev., Texas Instruments Inc., Dallas, TX, USA

fYear

2003

fDate

30 March-4 April 2003

Firstpage

208

Lastpage

213

Abstract

Electrical instability due to charge trapping in high-k materials is a primary concern for the usefulness of these films in future CMOS devices. This paper reports the effect of charge trapping on the threshold voltage and transistor drive current of devices made with HfSiON gate dielectric. Our results show that the physics of the charge trapping in HfSiON is unique and follows logarithmic dependence with time rather than usual exponential dependence. NMOS devices fabricated with HfSiON films show acceptable electrical stability for 10 years without substantial degradation of either the threshold voltage or the drive current.

Keywords

CMOS integrated circuits; MOSFET; dielectric thin films; hafnium compounds; interface states; semiconductor device reliability; semiconductor device testing; silicon compounds; 1.2 V; 10 year; 105 C; CMOS devices; HfSiON; HfSiON gate dielectrics; NMOS devices; acceptable electrical stability; charge trapping; electrical instability; high-k materials; interface state charge; logarithmic time dependence; positive biased temperature stress stability; threshold voltage; transistor drive current; trapped oxide charge; Degradation; Dielectric devices; High K dielectric materials; High-K gate dielectrics; MOS devices; Physics; Stability; Stress; Temperature; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium Proceedings, 2003. 41st Annual. 2003 IEEE International

Print_ISBN

0-7803-7649-8

Type

conf

DOI

10.1109/RELPHY.2003.1197747

Filename

1197747