Competing hot carrier degradation mechanisms in lateral n-type DMOS transistors

In this paper, the hot carrier degradation behaviour of a lateral nDMOS, processed in a 0.35 μm compatible Smart Power Technology, is presented. It is shown that upon reverse bias stress, two different and competing degradation mechanisms occur. An attempt is made to identify the two mechanisms by analysis of the electrical data and by performing Charge Pumping (CP) experiments and TCAD simulations. A first mechanism is attributed to a decreased electron mobility due to increased carrier scattering upon Dit formation in the channel, whereas the second mechanism occurs in the gate overlapped drift region of the device and is due to hot-hole injection and trapping. The competition of both mechanisms depends strongly on the stress conditions. A model is presented.