DocumentCode :
3437726
Title :
A High-Performance Energy-Efficient Hybrid Redundant MAC for Error-Resilient Applications
Author :
Dutt, S. ; Chauhan, A. ; Bhadoriya, R. ; Nandi, S. ; Trivedi, G.
Author_Institution :
Dept. of Electron. & Electr. Eng., Indian Inst. of Technol. Guwahati, Guwahati, India
fYear :
2015
fDate :
3-7 Jan. 2015
Firstpage :
351
Lastpage :
356
Abstract :
In the majority of Digital Signal Processing (DSP) applications, such as image, audio and video processing, the final result is interpreted by human senses, and, the fact of confined perception of human senses declines the strict restriction on accuracy. Thus, by adopting the emerging concept of approximate computing, we propose an approximate radix-2 hybrid redundant Multiply-and-Accumulate (Approx MAC) unit which stems a novel Speed-Power-Accuracy-Area (SPAA) metrics. The Approx MAC unit attains tremendous improvements in computational performance, energy efficiency and silicon area with a trivial degradation in the output quality. To inspect the effectiveness of the proposed approach in real-time DSP applications, we demonstrate an Approx MAC unit embedded JPEG-E-X IP core architecture. The Approx MAC unit with 40 approximate LSBs ensures 7.177x and 1.526x speedup, 1.594x and 4.163x energy efficiency, and 1.131x and 1.277x silicon area improvements over binary and hybrid redundant MAC units, respectively. Moreover, the Approx MAC unit with 40 approximate LSBs decorates power precision and delay-precision metrics by 14.71% and 32.95%, respectively.
Keywords :
approximation theory; digital arithmetic; digital signal processing chips; Approx MAC unit; DSP; SPAA metrics; approximate computing; approximate radix-2 hybrid redundant multiply-and-accumulate unit; digital signal processing; embedded JPEG-E-X IP core architecture; error-resilient applications; high-performance energy-efficient hybrid redundant MAC; multiply-and-accumulate operation; speed-power-accuracy-area metrics; Adders; Approximation algorithms; Approximation methods; Computer architecture; Digital signal processing; Measurement; Silicon; Approximate Computing; Error Resilient Application; Hybrid Redundant Number System; Multiply-and-Accumulate Unit;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design (VLSID), 2015 28th International Conference on
Conference_Location :
Bangalore
ISSN :
1063-9667
Type :
conf
DOI :
10.1109/VLSID.2015.65
Filename :
7031759
Link To Document :
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