Title :
Efficacy of port and lane staggering in reducing IO power supply noise
Author :
Govindan, S. ; Venkataraman, S.
Author_Institution :
Intel Technol. India Private Ltd., Bangalore, India
Abstract :
IO supply noise reduction techniques such as Port and Lane staggering have been introduced in the 32nm Intel server CPU (code named Westmere-EX) to improve the IO link performance. The post-silicon efficacy of these noise reduction techniques have been measured and are presented here.
Keywords :
computer interfaces; multiprocessing systems; power supplies to apparatus; I-O power supply noise reduction; IO link performance; Intel server CPU; lane staggering; port staggering; post-silicon efficacy; Delay; Noise; Noise measurement; Ports (Computers); Resonant frequency; Training; Transmitters;
Conference_Titel :
Electrical Design of Advanced Packaging and Systems Symposium (EDAPS), 2012 IEEE
Conference_Location :
Taipei
Print_ISBN :
978-1-4673-1444-2
Electronic_ISBN :
978-1-4673-1445-9
DOI :
10.1109/EDAPS.2012.6469416
