Automatic layout and optimization of static CMOS cells

Author

Mailhot, FrtdCric ; DeMicheli, Giovanni

Author_Institution

Dept. of Electr. Eng., Stanford Univ., Palo Alto, CA, USA

fYear

1988

fDate

3-5 Oct 1988

Firstpage

180

Lastpage

185

Abstract

A novel algorithm for generating complex CMOS gates from Boolean factored forms is presented. It uses a hierarchical composition of cells corresponding to the subexpressions of a Boolean factored form. Composition rules that allow for constructing the gates in linear time are derived. Cell width/height tradeoffs are made possible to ease pitch-matching. The algorithm has been coded in a pair of programs, called Castor and Pollux. The programs have been used to generate moderately complex layouts, consisting of circuits having up to a few thousand transistors. They can also be used to automatically generate a library of logic gates

Keywords

CMOS integrated circuits; circuit layout CAD; integrated logic circuits; logic CAD; Boolean factored forms; Castor; Pollux; automatic layout; composition rules; hierarchical composition of cells; optimization; static CMOS cells; Automatic logic units; CMOS logic circuits; CMOS technology; Circuit synthesis; Heuristic algorithms; Logic arrays; Logic circuits; Logic design; Logic gates; Software libraries;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1988. ICCD '88., Proceedings of the 1988 IEEE International Conference on

Conference_Location

Rye Brook, NY

Print_ISBN

0-8186-0872-2

Type

conf

DOI

10.1109/ICCD.1988.25686

Filename

25686