Increasing the ESD protection capability of over-voltage NMOS structures by comb-ballasting region design

Author

Vashchenko, V.A. ; Concannon, A. ; ter Beek, M. ; Hopper, P.

Author_Institution

Nat. Semicond. Corp., Santa Clara, CA, USA

fYear

2003

fDate

30 March-4 April 2003

Firstpage

261

Lastpage

268

Abstract

The objective of this study is to find a generic design solution for the cascoded snapback NMOS that delivers robust operation and eliminates the requirement for an additional ESD implant. In addition, the research goal of this study is to understand the physical failure mechanism, taking into account the non-linear effects of NMOS snapback, and to provide, at a minimum, a phenomenological explanation of the observed trends resulting from the analysis of Si based experiments.

Keywords

CMOS integrated circuits; MOSFET; electrostatic discharge; failure analysis; overvoltage protection; semiconductor device breakdown; semiconductor device reliability; semiconductor device testing; 0.18 micron; ESD protection capability; NMOS snapback; Si based experiments; breakdown; cascoded snapback NMOS; comb-ballasting region design; conductivity modulation; generic design solution; nonlinear effects; over-voltage NMOS structures; phenomenological explanation; physical failure mechanism; robust operation; silicided 0.18 μm CMOS technology; triggering; CMOS technology; Conductivity; Electrostatic discharge; Failure analysis; Implants; MOS devices; Protection; Robustness; Substrates; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium Proceedings, 2003. 41st Annual. 2003 IEEE International

Print_ISBN

0-7803-7649-8

Type

conf

DOI

10.1109/RELPHY.2003.1197755

Filename

1197755