The failure mechanism of high voltage tolerance IO buffer under ESD

In this paper, real-time I-V measurements and TCAD simulations were used to study why the ESD performance of the HVT I/O circuit is different from that of the ST NMOS device. The real-time I-V measurements show that the top gate induced voltage of the ST NMOS in HVT I/O circuits under an ESD zapping event is much higher than that of the ST NMOS device. The simulations show that high gate voltage will induce current crowding in the channel region, so as to degrade the device ESD performance. This phenomenon is called "gate voltage-induced current crowding" (GVICC). However, it is also found that the use of non-silicide S/D structures and increasing RPO dimensions at the drain region of the top NMOSFET can effectively reduce the GVICC effect and induce the currents to flow through the bulk parasitic bipolar transistor. As a result, the ESD failure threshold can be much improved.