DocumentCode :
3437824
Title :
Programmable Motion Estimation architecture
Author :
Drolapas, Anargyros ; Lentaris, George ; Reisi, Dionysios
Author_Institution :
Dpt of Phys., Nat. & Kapodistrian Univ. of Athens, Athens, Greece
fYear :
2009
fDate :
13-16 Dec. 2009
Firstpage :
323
Lastpage :
326
Abstract :
This paper presents a real-time Motion Estimation architecture with improved hardware cost. The design bases on a parallel memory organization minimizing the resources required to support integer and sub-pixel modes of search, while it sustains the required throughput of pixels to the SAD calculator. A speculative execution technique improves the number of cycles required by the search process. The architecture is programmable including an instruction set for actions common to all the block-matching techniques, while circuits introduced at compile time accommodate individual actions of the most demanding algorithms such as MVFAST and PMVFAST. A FPGA implementation validates HDTV video performance.
Keywords :
computer architecture; image processing equipment; instruction sets; motion estimation; parallel memories; parallel programming; FPGA implementation; HDTV video performance; PMVFAST; SAD calculator; block matching technique; instruction set; parallel memory organization; programmable motion estimation architecture; speculative execution technique; subpixel mode; Circuits; Computer architecture; Costs; Filters; HDTV; Hardware; Motion estimation; Pipelines; Read-write memory; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics, Circuits, and Systems, 2009. ICECS 2009. 16th IEEE International Conference on
Conference_Location :
Yasmine Hammamet
Print_ISBN :
978-1-4244-5090-9
Electronic_ISBN :
978-1-4244-5091-6
Type :
conf
DOI :
10.1109/ICECS.2009.5411005
Filename :
5411005
Link To Document :
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