Impact of TSV induced thermo-mechanical stress on semiconductor device performance

Evaluation of the impact caused by Through-Silicon Vias (TSV) induced thermo-mechanical stress on device performance is becoming important due to the close proximity between TSVs and the semiconductor devices in 3D integration. From the literatures, there exist discrepancies between theory, simulated and experimental results presented. For accurate predictions, we simulated stress build-up by taking the full CMOS process flow into consideration. We considered the interaction between TSV, stressors such as tensile stress liner and Shallow Trench Isolation (STI) and device channel. From the results, it was found that the nMOSFET I_on variation is less than 2% at Keep Out Zone (KOZ) of 1 μm due to TSV induced stress while the I_on variation is about 30% due to the tensile stress liner. Hence, the impact of TSV induced stress on nMOSFET performance is insignificant compared to that of tensile stress liner in the device.