Evaluating a Hardware-Based Approach for Detecting Resistive-Open Defects in SRAMs

Advances in Very Deep Sub-Micron (VDSM) technology have made possible the integration of millions of transistors into a small area and consequently, has increased the circuit´s density. The increase of Nano-Scale Static Random Access Memories (SRAMs) density has become an important concern for testing, since generated new types of defects that can occur during the manufacturing process. The rapidly increasing need to store more information results in the fact that the memory elements occupy great part of the System-on-Chip´s (SoC) silicon area. In this context, the present paper describes and evaluates a technique based on On-Chip Current Sensors (OCCS) and Neighbourhood Comparison Logic (NCL) to detect resistive-open defects in SRAMs. Experimental results obtained throughout simulations demonstrate the technique´s efficiency as well as its behaviour considering process variation. To conclude, an analysis of the overheads makes possible the comparison with today´s standard techniques.