Title :
Approaching a nanosecond: a 32 bit adder
Author :
Bewick, Gary ; Song, Paul ; De Micheli, Giovaiini ; Flynn, Michael J.
Author_Institution :
Comput. Syst. Lab., Stanford Univ., CA, USA
Abstract :
The authors describe a high performance 32-bit binary adder designed at Stanford University. Measurements indicate that the adder computes the sum of two numbers (and a carry) in 2.1 ns and consumes 900 mW, using a power-supply voltage of -4.5 V. The adder is implemented using silicon emitter-coupled-logic circuitry with 0.5-V output swings. The high performance is a result of high-speed logic/technology and a special addition algorithm which results in an adder with a maximum of three levels of logic from any input to any output. The maximum fanout on any signal is eight input loads, the maximum number of inputs on any gate is five, and the maximum number of WIRE-OR outputs is eight
Keywords :
adders; bipolar integrated circuits; emitter-coupled logic; 2.1 ns; 32 bit; 32 bit adder; 900 mW; binary adder; silicon emitter-coupled-logic circuitry; Adders; Circuits; Computer networks; Delay; High performance computing; Laboratories; Logic; Power measurement; Power supplies; Silicon;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1988. ICCD '88., Proceedings of the 1988 IEEE International Conference on
Conference_Location :
Rye Brook, NY
Print_ISBN :
0-8186-0872-2
DOI :
10.1109/ICCD.1988.25695
