A comparison of two digit serial VLSI adders

Author

Irwin, Mary Jane ; Owens, Robert Michael

Author_Institution

Dept. of Comput. Sci., Pennsylvania State Univ., University Park, PA, USA

fYear

1988

fDate

3-5 Oct 1988

Firstpage

227

Lastpage

229

Abstract

The VLSI design of two digit serial adders, one which processes operand digits and produces online result digits least-significant digit first, and one which processes operands and produces online result digits most-significant digit first, is presented. They are compared with respect to number of gates, interconnect lines, layout area, and digit and operand add time. An optimal gate level description suitable for static CMOS implementation for one of the adders is given. This gate-level description can be input to a layout tool to automatically produce the CMOS gate matrix layout of the description. Finally, word-parallel adders built out of the two digit serial adders are discussed and compared

Keywords

CMOS integrated circuits; VLSI; adders; add time; gate matrix layout; interconnect lines; layout area; operand digits; static CMOS implementation; two digit serial VLSI adders; word-parallel adders; CMOS integrated circuits; Clocks; Cloning; Computer science; Delay; Encoding; Load flow control; Logic; Tin; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1988. ICCD '88., Proceedings of the 1988 IEEE International Conference on

Conference_Location

Rye Brook, NY

Print_ISBN

0-8186-0872-2

Type

conf

DOI

10.1109/ICCD.1988.25696

Filename

25696