• DocumentCode
    3437948
  • Title

    Performance and complexity of block turbo decoder circuits

  • Author

    Adde, Patrick ; Pyndiah, Ramesh ; Raoul, Olivier

  • Author_Institution
    Telecom Bretagne, Brest, France
  • Volume
    1
  • fYear
    1996
  • fDate
    13-16 Oct 1996
  • Firstpage
    172
  • Abstract
    This paper presents the latest results on block turbo codes and also an analysis of the possible implementations of a block turbo decoder circuit. Simulation results show that the SNR (signal to noise ratio) required to achieve a BER (Bit Error Rate) of 10-5 with block turbo codes is 2.5±0.2 dB from their Shannon limit for any code rate. We have identified three different solutions for implementing the block turbo decoder circuit. After discussing the advantages and disadvantages of the different solutions, we give the results of the degradation of the performance of the block turbo decoder circuit due to data quantization. Finally, in our conclusion, we discuss how to reduce the complexity of the algorithm for its implementation
  • Keywords
    block codes; decoding; error correction codes; iterative methods; quantisation (signal); SNR; Shannon limit; bit error rate; block turbo decoder circuits; code rate; data quantization; iterative methods; performance degradation; signal to noise ratio; Block codes; Circuits; Concatenated codes; Convolutional codes; Iterative algorithms; Iterative decoding; Maximum likelihood decoding; Product codes; Signal to noise ratio; Turbo codes;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronics, Circuits, and Systems, 1996. ICECS '96., Proceedings of the Third IEEE International Conference on
  • Conference_Location
    Rodos
  • Print_ISBN
    0-7803-3650-X
  • Type

    conf

  • DOI
    10.1109/ICECS.1996.582746
  • Filename
    582746