McMAP: a fast technology mapping procedure for multi-level logic synthesis

Author

Lisanke, Robert ; Brglez, Franc ; Kedem, Gershon

Author_Institution

Microelectron. Center of North Carolina, Research Triangle Park, NC, USA

fYear

1988

fDate

3-5 Oct 1988

Firstpage

252

Lastpage

256

Abstract

The authors present a method for transforming multilevel equations into a gate-level netlist of a given technology. The proposed mapping procedure performs multiple mappings, each with randomly selected program parameters. The number of mappings is user-settable, and it offers the designer an option to trade off CPU runtime for better results. This feature is important to designers who begin by exploring the space of architectural possibilities, then finally create a specific, highly optimized circuit. The proposed technology mapping method has been implemented in C as a logic-design tool (McMAP) that takes full advantage of any gate library´s timing and area information. Using default parameter settings, the tool synthesized several standard benchmark examples yielding higher-quality circuits with lower CPU requirements than previously reported

Keywords

logic CAD; many-valued logics; C; McMAP; default parameter settings; fast technology mapping procedure; gate-level netlist; multilevel logic synthesis; Automatic logic units; Boolean functions; CMOS logic circuits; Circuit synthesis; Equations; Logic design; Logic testing; Network synthesis; Space technology; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1988. ICCD '88., Proceedings of the 1988 IEEE International Conference on

Conference_Location

Rye Brook, NY

Print_ISBN

0-8186-0872-2

Type

conf

DOI

10.1109/ICCD.1988.25701

Filename

25701