Rectilinear Steiner Clock Tree Routing Technique with Buffer Insertion in Presence of Obstacles

Clock tree design plays a significant role in determining chip performance and requires serious involvement for designing a critical VLSI circuit. Algorithms to design clocked net involve complexities of memory and time along with the physical design constraints. In this work an efficient algorithm, BBLUE (Blockage Look Up and Buffer Estimation) is designed, which routes all the sinks in two phases. First routing in the global domain is achieved after tiling process and then routing in the local domain is done by connecting all the sinks inside a tile and combining the routes of all the tiles. Further in this work, BBLUE avoids the obstacles by snaking of wire with Steiner point insertion and the skew minimization is achieved by restricted buffer insertion in an efficient way. BBLUE is tested on ISPD 2010 benchmark suite and performance wise it is a better performer in certain parameters compared to its contenders of the benchmark suite provided by Intel and IBM.