Mapping properties of multi-level logic synthesis operations

It was found that synthesis operations like kernel extraction-intersection and phase assignment have excellent mapping properties in the synthesis of multilevel Boolean networks when a symmetric (dual) target library of standard cells is used. This was made possible by DIRMAP, a simple translator of the optimized and properly decomposed set of Boolean functions, which produces 4 to 12% better area results than those obtained with more complex mappers based on tree-matching techniques. Using the logic optimizer MIS, experiments were run over a wide range of benchmarks and industrial examples and a symmetric, negative-logic two-level standard cell library with fan-in constraint of four was used as a target technology. Complete statistics of the trees composing each of the optimized Boolean networks are presented