• DocumentCode
    3438066
  • Title

    Geometric Programming Formulation for Gate Sizing with Pipelining Constraints

  • Author

    Naidu, S.R.

  • Author_Institution
    Int. Inst. of Inf. Technol., Bangalore, India
  • fYear
    2015
  • fDate
    3-7 Jan. 2015
  • Firstpage
    452
  • Lastpage
    457
  • Abstract
    We propose a novel framework to solve the combined retiming/gate sizing problem in the context of optimization of acyclic pipelines. The adjustment of sizes to gates in a combinational circuit is a continuous problem, solvable by a variety of convex optimization tools provided the delay model for each gate is placed in a convex framework. Retiming is a discrete problem since it involves physically moving registers from one location to another. In this paper, we enhance an existing convex optimization framework proposed by Boyd et al [1] to handle registers as 0-1 variables. We solve the relaxed formulation as a geometric program and glean valuable information about the circuit´s performance. Another significant contribution of our paper is that we show that our problem is NP-hard.
  • Keywords
    combinational circuits; computational complexity; convex programming; flip-flops; geometric programming; sizing (materials processing); NP-hard problems; acyclic pipelining constraint optimization; combinational circuit performance; combined retiming-gate sizing problem; convex optimization tool framework; delay model; geometric programming formulation; glean valuable information; physically moving registers; Capacitance; Delays; Linear programming; Logic gates; Pipeline processing; Registers; Resistance; NP-hard; convex optimization; gate sizing; retiming;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design (VLSID), 2015 28th International Conference on
  • Conference_Location
    Bangalore
  • ISSN
    1063-9667
  • Type

    conf

  • DOI
    10.1109/VLSID.2015.82
  • Filename
    7031776