Classical fault analysis for MOS VLSI circuits

Due to the high cost associated with generating effective input vectors to test MOS circuits, finding ways to reduce this test vector generation cost is of considerable interest. Empirical results show that fault coverage obtained from MOS transistor-level fault simulation using randomly generated test inputs can be approximated by the fault coverage obtained using the test vectors generated from classical stuck-at-zero and stuck-at-one fault simulation on logic-gate-level circuits. Applying this result, an approach is presented to reduce the cost of test vector generation for MOS circuits