Investigation of wafer level burn-in to SoC memory: 1TRAM

Author

Pan, Y.L. ; Chen, S.H. ; Lu, C.H. ; Wang, J.J.

Author_Institution

Taiwan Semicond. Manuf. Corp, Hsin-Chu, Taiwan

fYear

2003

fDate

30 March-4 April 2003

Firstpage

391

Lastpage

394

Abstract

This paper investigates the effect of Wafer Level Burn-In (WLBI) on retention time of 1TRAMs by using a simple and practical gate oxide stress method. We find that the WLBI stress time does not influence the degradation of retention time when we continue to increase the stress time beyond 40 s in WLBI. We try to clarify retention time degradation in long term WLBI by experiments. A 1TRAM memory is utilized to ascertain whether the WLBI mode is successfully implemented or not. Moreover, the WLBI method is compared with traditional Package Level Burn-In (PLBI). By using WLBI, gate oxide defects in 1TRAM cell arrays can be screened in CP (Chip Probing) testing and the method can be applied to other memory products.

Keywords

CMOS memory circuits; DRAM chips; MOS capacitors; cellular arrays; failure analysis; integrated circuit reliability; integrated circuit testing; semiconductor device breakdown; system-on-chip; 0.18 micron; 1TRAM; 1TRAM cell array; SoC memory; TDDB test; chip probing testing; gate oxide defect; gate oxide stress method; memory products; package level burn-in; planar DRAM cell; retention time degradation; silicide gate MOS capacitor; stress time; wafer level burn-in; Costs; DRAM chips; Geometry; Life testing; MOS capacitors; Random access memory; Space technology; Stress; Temperature; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium Proceedings, 2003. 41st Annual. 2003 IEEE International

Print_ISBN

0-7803-7649-8

Type

conf

DOI

10.1109/RELPHY.2003.1197779

Filename

1197779