Chip-package-PCB co-design: Dealing with harmonic desensitization in RF SoC/SiP

A comprehensive study based on chip-package-PCB co-design is presented to deal with the harmonic desensitization issue in RF receivers. To gain insights on the interaction between the chip, interconnects, and harmonic interferences, simplified interconnect models were co-simulated with the crystal oscillator as well as the posterior buffer chain to realize the mutual dependency. It was found that decoupling mechanism and interconnect parasitics will dominate the harmonic leakage from the crystal oscillator chain. By optimizing the decoupling and interconnect parasitics, the desensitization phenomenon can be eliminated completely. This generalized analysis can widely be applied to all kinds of system-on-chip (SoC) / system-in-package (SiP) designs for wireless communication applications, in which interferences and couplings are critical bottlenecks of system integrations.