• DocumentCode
    3438299
  • Title

    Analysis of Second-Order Effect Components of Drain Conductance and Its Implication on Output Resistance of Wilson Current Mirror

  • Author

    Singh, K. ; Bhattacharyya, A.B.

  • Author_Institution
    Dept. of Electron. & Commun. Eng. & Center for MEMS Design, Jaypee Inst. of Inf. Technol., Noida, India
  • fYear
    2015
  • fDate
    3-7 Jan. 2015
  • Firstpage
    529
  • Lastpage
    534
  • Abstract
    Drain conductance gds is an important small signal parameter for analysis of small signal model of analog circuits as it influences the output resistance and voltage gain. The gds or reciprocal rds and Early voltage is a useful design parameter for designer as they appear frequently in intrinsic voltage gain and transresistance expression in general circuits. In this paper we analyze the different component of gds in which it can be decomposed to fifferent component as it is influenced by many second order effects like channel length modulation, vertical field mobility reduction, drain induced barrier lowering and velocity saturation. The analysis of impact of overdrive voltage and Inversion Coefficient (IC) for fixed drain voltage and shape factor on gds components is investigated. The validation of total drain conductance which is sum of its component is verified using BSIM3v3 model PTM generated data on 180nm technology node. The effect of component is shown in intrinsic voltage gain of single stage common source transistor and output resistance of Wilson current mirror as function of inversion level. The sensitivity of output resistance on process related parameters which give deeper insight of circuit performance is computed qualitatively. The interpolation equation as used by EKV model is taken for analysis and analytically computed for the different gds components.
  • Keywords
    analogue circuits; current mirrors; electric admittance; interpolation; modulation; sensitivity analysis; BSIM3v3 model PTM; CLM; DIBL; EKV model; Early voltage; IC; VFMR; Wilson current mirror resistance; analog circuit; channel length modulation; drain conductance; drain induced barrier lowering; fixed drain voltage; interpolation equation; intrinsic voltage gain; inversion coefficient; inversion level function; overdrive voltage; predictive technology model; resistance sensitivity; second-order effect component analysis; shape factor; single stage common source transistor; size 180 nm; small-signal model analysis; transresistance expression; velocity saturation; vertical field mobility reduction; Equations; Integrated circuit modeling; Logic gates; Mathematical model; Mirrors; Resistance; DIBL; VFMR; channel length modulation; drain conductance subcomponents; intrinsic voltage gain; inversion coefficient; output resistance; sensitivity analysis; velocity saturation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design (VLSID), 2015 28th International Conference on
  • Conference_Location
    Bangalore
  • ISSN
    1063-9667
  • Type

    conf

  • DOI
    10.1109/VLSID.2015.95
  • Filename
    7031789