• DocumentCode
    3438329
  • Title

    A high speed static CMOS PLA architecture

  • Author

    Engeler, William E. ; Lowy, Menahem ; Pedicone, John ; Bloomer, John ; Richotte, James ; Chan, David

  • Author_Institution
    General Electric Co., Schenectady, NY, USA
  • fYear
    1988
  • fDate
    3-5 Oct 1988
  • Firstpage
    348
  • Lastpage
    351
  • Abstract
    A static CMOS programmable-logic-array (PLA) architecture has been developed that enables the realization of high-speed control circuits while at the same time providing the low static power consumption inherent in CMOS technology. The PLA uses a novel circuit configuration and a two-phase clock to latch data between the AND and the OR planes. An 8-input, 13-output, 42-minterm finite state machine has been realized using an automatic generating system, in an area of 0.36 mm2. This structure operates from near DC to above 80 MHz
  • Keywords
    CMOS integrated circuits; integrated logic circuits; logic arrays; AND; OR planes; automatic generating system; finite state machine; high-speed control circuits; static CMOS PLA architecture; two-phase clock; Automata; CMOS logic circuits; Clocks; Ice; Latches; Logic arrays; Logic devices; MOS devices; Programmable logic arrays; Research and development;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design: VLSI in Computers and Processors, 1988. ICCD '88., Proceedings of the 1988 IEEE International Conference on
  • Conference_Location
    Rye Brook, NY
  • Print_ISBN
    0-8186-0872-2
  • Type

    conf

  • DOI
    10.1109/ICCD.1988.25720
  • Filename
    25720
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3438329