DocumentCode :
3438348
Title :
Soft breakdown in thin gate oxide - a measurement artifact
Author :
Cheung, Kin P.
Author_Institution :
Rutgers Univ., Piscataway, NJ, USA
fYear :
2003
fDate :
30 March-4 April 2003
Firstpage :
432
Lastpage :
436
Abstract :
Experimental evidence is reported here to show that the often-reported soft breakdown in ultra thin gate oxides under electrical stress is likely an experimental artifact induced by the inability to eliminate the current surge at the moment of the formation of a percolation path. Soft breakdown may not happen in real circuit under normal operation. Thus the percolation model will not be suitable for gate oxide reliability projections. Instead, model calculation of total SILC including multi-trap assisted tunneling at very high trap density will be more relevant to gate oxide reliability.
Keywords :
MOSFET; dielectric thin films; leakage currents; percolation; semiconductor device breakdown; semiconductor device measurement; semiconductor device reliability; tunnelling; CMOS technology transistors; current surge elimination; electrical stress; experimental artifact; gate oxide reliability projections; multi-trap assisted tunneling; percolation model; percolation path; plasma charging stress; soft breakdown; total SILC; ultra thin gate oxides; very high trap density; Breakdown voltage; CMOS technology; Circuits; Electric breakdown; Plasma devices; Plasma temperature; Semiconductor device modeling; Stress; Surges; Switches;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Reliability Physics Symposium Proceedings, 2003. 41st Annual. 2003 IEEE International
Print_ISBN :
0-7803-7649-8
Type :
conf
DOI :
10.1109/RELPHY.2003.1197786
Filename :
1197786
Link To Document :
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