A matched-delay CMOS TDM multiplexer cell

Standard time-division multiplexer circuits use variations on a finite-state-machine approach to sequence through all input data. The authors present an alternate multiplexer architecture that avoids both the bottleneck of waiting for latches to settle and the problems of distributing a high-frequency clock signal. The authors have investigated the tradeoffs between various architectures by fabricating and testing a CMOS implementation of both a matched-delay and shift-register-based architecture. Experiments show that the proposed approach can be competitive, but additional experiments are needed to further understand its practical limits