DocumentCode
3438385
Title
Microarchitecture of the 80960 high-integration processors
Author
Hinton, Glenn ; Lai, Konrad ; Steck, Randy
Author_Institution
Intel Corp., Hillsboro, OR, USA
fYear
1988
fDate
3-5 Oct 1988
Firstpage
362
Lastpage
365
Abstract
The 80960 is Intel Corporation´s newest microprocessor and serves as the first implementation of a novel architecture family. Design goals of the processor and architecture were to maintain a constant cost/benefit ratio in the entire design while identifying and minimization bottlenecks in an overall system architecture. This has resulted in an architecture suited to future proliferation as well as a first implementation with high functionality and good performance. The authors describe the microarchitecture of the 80960 processor and the tradeoffs made in its development to meet the design goals. Features discussed include the instruction decode and sequencing, the integer execution unit, the floating-point execution unit, and the translation lookaside buffer
Keywords
computer architecture; microprocessor chips; Intel 80960 microprocessor; floating-point execution unit; instruction decode; integer execution unit; microarchitecture; sequencing; translation lookaside buffer; Communication system control; Computer architecture; Decoding; Logic; Microarchitecture; Microprocessors; Pipelines; Prefetching; Process design; Registers;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 1988. ICCD '88., Proceedings of the 1988 IEEE International Conference on
Conference_Location
Rye Brook, NY
Print_ISBN
0-8186-0872-2
Type
conf
DOI
10.1109/ICCD.1988.25723
Filename
25723
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