Title :
Integrated design and test synthesis
Author :
Gebotys, Catherine H. ; Elmasry, Mohamed I.
Author_Institution :
Dept. of Electr. Eng., Waterloo Univ., Ont., Canada
Abstract :
An integrated design and test synthesis methodology is presented with area, delay, and test cost constraints. This methodology, called CATREE2, differs from other approaches by simultaneously synthesizing the normal and test mode design behavior. It is particularly suited for top-down system design where a VLSI component´s behavior and test method have been fully specified. Preliminary results show that better design solutions are obtained by considering test incorporation during design synthesis than other methods which incorporate test after a structural design solution is formed
Keywords :
VLSI; circuit CAD; software tools; CATREE2; VLSI; area constraints; delay constraints; design solutions; integrated design synthesis; test cost constraints; test synthesis; top-down system design; Algorithm design and analysis; Costs; Delay estimation; Design methodology; Feedback; Hardware; Stress; System testing; Topology; Very large scale integration;
Conference_Titel :
Computer Design: VLSI in Computers and Processors, 1988. ICCD '88., Proceedings of the 1988 IEEE International Conference on
Conference_Location :
Rye Brook, NY
Print_ISBN :
0-8186-0872-2
DOI :
10.1109/ICCD.1988.25731
