An enhanced erase mechanism in flash memory and its implication on endurance reliability

Author

Tseng, Jermyn M Z ; Larsen, B.J. ; Xiao, Y. ; Yount, J. ; Randazzo, T. ; Shore, S. ; Miller, G. ; Erickson, D.A.

Author_Institution

Atmel Corp., Colorado Springs, CO, USA

fYear

2003

fDate

30 March-4 April 2003

Firstpage

513

Lastpage

517

Abstract

An enhanced erase mechanism in flash memory by increasing the generation of holes via impact ionization is described. The endurance degradation associated with this erase mechanism is found to be different from those using the conventional source-side erase methods, as the better erase margin and worse program degradation are observed. The improvement of erase margin is then investigated by using a special cell structure with access to the floating gate and is explained in terms of injection efficiency of hot holes. This erase mechanism also has an impact on the data retention results due to the enhanced generation of holes.

Keywords

CMOS memory circuits; flash memories; hot carriers; impact ionisation; integrated circuit reliability; integrated circuit testing; tunnelling; band-to-band tunneling; cell structure; endurance degradation; endurance reliability; enhanced erase mechanism; erase margin; flash memory; floating gate; hole generation; hot hole injection efficiency; impact ionization; program degradation; Charge carrier processes; Degradation; Electron emission; Flash memory; Hot carriers; Impact ionization; Nonvolatile memory; Springs; Tunneling; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium Proceedings, 2003. 41st Annual. 2003 IEEE International

Print_ISBN

0-7803-7649-8

Type

conf

DOI

10.1109/RELPHY.2003.1197801

Filename

1197801