Decentralized BIST for 1149.1 and 1149.5 based interconnects

Author

Su, Chauchin ; Jou, Shyh-Jye ; Yuan-Tzu Ting

Author_Institution

Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan

fYear

1996

fDate

11-14 Mar 1996

Firstpage

120

Lastpage

125

Abstract

This paper presents a decentralized BIST methodology for system level interconnects. For 3-state nets we interleave pseudorandom counting sequences (PCS) and walking sequences to avoid the conflict among multiple drivers of a net. For multiple scan chains each chain is applied with a particular window of the PCS to ensure the distinctness of every test vector and 100% stuck-at and short faults coverage for nets across scan chains and/or board boundaries. The synchronization of chains of different lengths is handled gracefully by inserting a preamble to make all the chains the same length

Keywords

IEEE standards; automatic testing; binary sequences; boundary scan testing; built-in self test; fault diagnosis; packaging; decentralized BIST; multiple drivers; multiple scan chains; pseudorandom counting sequences; scan chains; short faults; stuck-at faults; system level interconnects; test vector; walking sequences; Automatic testing; Built-in self-test; Centralized control; Control systems; Electronic equipment testing; Fixtures; Legged locomotion; Packaging; Personal communication networks; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

European Design and Test Conference, 1996. ED&TC 96. Proceedings

Conference_Location

Paris

ISSN

1066-1409

Print_ISBN

0-8186-7424-5

Type

conf

DOI

10.1109/EDTC.1996.494136

Filename

494136