Reliability issues and advanced failure analysis deprocessing techniques for copper/low-k technology

With technology continually scaling down, Cu/low-k technology has been introduced to reduce interconnect resistance, improve electromigration resistance and reduce cross talk effects. In this paper, we discuss new failure modes, reliability issues and failure analysis (FA) challenges for copper technology. Several FA deprocessing techniques are discussed: wet chemical etching, reactive ion etching (RIE), parallel polishing, chemical mechanical polishing (CMP) and a combination of these techniques. Specific details are given of RIE process characterization and optimization for several inter-level dielectrics to attain high etch selectivity, free of RIE grass. We find the combination of CMP and RIE deprocessing techniques works well in most situations for copper technologies. Cross-section analysis of copper devices is also discussed. The development of reproducible backside silicon sample preparation techniques has become increasingly important to accurately localize defects for Cu/low-k technology. Several backside sample preparation techniques are described including mechanical milling, RIE and wet chemical etching. Finally, some FA case studies of Cu/low-k devices are presented.