A high level synthesis tool for massively parallel image processing ASICs

Author

Boubekeur, A. ; Saucier, G.

Author_Institution

Inst. Nat. Polytech. de Grenoble, France

fYear

1991

fDate

13-16 May 1991

Firstpage

53

Lastpage

57

Abstract

An automatic design methodology for massively parallel architectures for low-level image processing is presented. The system takes as input a high-level description of the algorithm. It generates an optimized circuit organized as a SIMD mesh connected array of 1-bit processing elements with minimized resources

Keywords

CMOS integrated circuits; computerised picture processing; digital signal processing chips; parallel architectures; 1-bit processing elements; SIMD mesh connected array; automatic design methodology; high level synthesis tool; high-level description; low-level image processing; massively parallel architectures; massively parallel image processing; optimized circuit; Application specific integrated circuits; Design methodology; Face; High level synthesis; High performance computing; Image processing; Integrated circuit synthesis; Mesh generation; Parallel architectures; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

CompEuro '91. Advanced Computer Technology, Reliable Systems and Applications. 5th Annual European Computer Conference. Proceedings.

Conference_Location

Bologna

Print_ISBN

0-8186-2141-9

Type

conf

DOI

10.1109/CMPEUR.1991.257355

Filename

257355