A method to comprehend the impact of interconnect coupling effects on gate oxide reliability

Author

Mutlu, Ayhan A. ; Aminzadeh, Payman

Author_Institution

Intel Corp., Santa Clara, CA, USA

fYear

2003

fDate

30 March-4 April 2003

Firstpage

570

Lastpage

571

Abstract

A method to quantify the interconnect coupling effects on gate oxide reliability is developed. Post-layout noise waveforms at each gate node are obtained by using TCAD noise simulation tools. These waveforms are used to determine an average time to fail (TTF), which is eventually used in gate oxide failure probability calculations. Additionally, the TTF is translated to a DC equivalent voltage (DCEV) for quantification of the coupling impact in terms of voltage.

Keywords

MOSFET; dielectric thin films; failure analysis; integrated circuit interconnections; overvoltage; semiconductor device breakdown; semiconductor device noise; semiconductor device reliability; technology CAD (electronics); DC equivalent voltage; MOS transistor; TCAD noise simulation tools; average time to fail; gate oxide failure probability calculations; gate oxide reliability; interconnect coupling effects; post-layout noise waveform; time-to-breakdown; voltage overshoots; Analytical models; Circuit noise; Circuit simulation; Coupling circuits; Degradation; Delay; Histograms; Integrated circuit interconnections; Stress; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium Proceedings, 2003. 41st Annual. 2003 IEEE International

Print_ISBN

0-7803-7649-8

Type

conf

DOI

10.1109/RELPHY.2003.1197810

Filename

1197810