Title :
A timing-constrained incremental routing algorithm for symmetrical FPGAs
Author :
Raman, Srilata ; Liu, C.L. ; Jones, L.G.
Author_Institution :
Adv. Design Technol., Motorola Inc., Austin, TX, USA
Abstract :
in this paper we present a timing-constrained routing algorithm for symmetrical FPGAs which embodies a novel incremental routing strategy that combines global and detailed routing, and a routing resource allocation algorithm that takes into account both the characteristics of the routing resources and timing information. Experimental results confirm that the algorithm reduces delay along the longest path in the circuit, uses routing resources efficiently, and requires low CPU time
Keywords :
field programmable gate arrays; integrated circuit layout; logic design; network routing; resource allocation; timing; circuit delay; detailed routing; global routing; resource allocation; symmetrical FPGAs; timing-constrained incremental routing algorithm; Delay estimation; Field programmable gate arrays; Integrated circuit interconnections; Logic arrays; Pins; Resource management; Routing; Switches; Symmetric matrices; Timing;
Conference_Titel :
European Design and Test Conference, 1996. ED&TC 96. Proceedings
Conference_Location :
Paris
Print_ISBN :
0-8186-7424-5
DOI :
10.1109/EDTC.1996.494144
