DocumentCode :
3438939
Title :
Asynchronous SRT dividers: the real cost
Author :
Boutamine, H. ; Guyot, A. ; Elhassan, B. ; Renaudin, M.
Author_Institution :
TIMA Lab., Inst. Nat. Polytech. de Grenoble, France
fYear :
1996
fDate :
11-14 Mar 1996
Firstpage :
195
Lastpage :
199
Abstract :
Synchronous systems represent the majority of digital circuits built, essentially because they are easier to design and test. However, asynchronous approaches are becoming more attractive to designers because of the potential advantages brought in terms of power consumption and delay, and also favoured by the increased sophistication of today´s CAD tools. An important topic in asynchronous research is the SRT (Sweeny, Robertson, Tocher) self-timed divider. In this paper we compare two versions of a 32-bit SRT divider, synchronous and asynchronous. Our results show that the asynchronous circuit is faster, but consumes more power over an increased area
Keywords :
asynchronous circuits; digital arithmetic; dividing circuits; timing; 32 bit; asynchronous SRT dividers; asynchronous circuit; self-timed divider; Asynchronous circuits; Circuit testing; Clocks; Costs; Delay; Design automation; Digital circuits; Energy consumption; Microprocessors; System performance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
European Design and Test Conference, 1996. ED&TC 96. Proceedings
Conference_Location :
Paris
ISSN :
1066-1409
Print_ISBN :
0-8186-7424-5
Type :
conf
DOI :
10.1109/EDTC.1996.494148
Filename :
494148
Link To Document :
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