Title :
Power optimization of delay constrained CMOS bus drivers
Author :
Caufape, S. ; Figueras, J.
Author_Institution :
Dept. d´´Enginyeria Electron., Univ. Politecnica de Catalunya, Barcelona, Spain
Abstract :
The design automation of minimum power delay-constrained CMOS Bus Drivers for library-based (standard cells) and full-custom design environments is presented in this paper. The effect of the short circuit current consumption is taken into account in the total power evaluation. The proposed methodology is applied to effectively find the optimum selection of buffers for any given bus load and delay constraint. Comparison with other strategies, such as constant taper or minimum power-delay solutions, show power savings of more than 100% using the proposed methodology. Analytical predictions and results show good agreement with time costly SPICE simulations and reflect the need of variable taper factors for low power buffers in synchronous CMOS digital circuits
Keywords :
CMOS logic circuits; buffer circuits; circuit CAD; circuit optimisation; delays; driver circuits; integrated circuit design; logic CAD; bus load; delay constrained CMOS bus drivers; delay constraint; full-custom design environment; library-based design environment; optimum buffer selection; power optimization; short circuit current consumption; standard cells; synchronous CMOS digital circuits; total power evaluation; variable taper factors; Analytical models; CMOS digital integrated circuits; Circuit simulation; Constraint optimization; Delay effects; Design automation; Driver circuits; Predictive models; SPICE; Short circuit currents;
Conference_Titel :
European Design and Test Conference, 1996. ED&TC 96. Proceedings
Conference_Location :
Paris
Print_ISBN :
0-8186-7424-5
DOI :
10.1109/EDTC.1996.494150
