Localization and analysis of functional failures in deep submicron advanced ASIC products

Author

Rubin, M.

Author_Institution

Agilent Technol., Fort Collins, CO, USA

fYear

2003

fDate

30 March-4 April 2003

Firstpage

588

Lastpage

589

Abstract

This paper proposes a complete methodology of localizing functional scan failures on complex custom ASIC designs without the need for special test development or use of specialized design debug equipment. The effectiveness of the methodology was proven in the foundry on several ASIC products from two different companies. The results of this work provided necessary information for the FAB manufacturing teams to understand the nature of the problem and resulted in process enhancements, which enabled the FAB to achieve significant yield improvement in record time.

Keywords

application specific integrated circuits; failure analysis; fault location; integrated circuit reliability; integrated circuit testing; integrated circuit yield; 0.18 micron; IC testing theory; complex custom ASIC designs; custom logic circuits; deep submicron advanced ASIC products; foundry; functional failure localization; process enhancements; yield improvement; Application specific integrated circuits; Circuit faults; Circuit testing; Data mining; Failure analysis; Foundries; Integrated circuit modeling; Logic testing; Manufacturing; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium Proceedings, 2003. 41st Annual. 2003 IEEE International

Print_ISBN

0-7803-7649-8

Type

conf

DOI

10.1109/RELPHY.2003.1197819

Filename

1197819