A balanced-mesh clock routing technique using circuit partitioning

Author

Sat, Hidenori ; Onozawa, Akira ; Matsuda, Hiroaki

Author_Institution

NTT LSI Labs., Kanagawa, Japan

fYear

1996

fDate

11-14 Mar 1996

Firstpage

237

Lastpage

243

Abstract

A clock routing technique using a balanced-mesh routing is proposed, which incorporates the advantages of both the well-known balanced-tree and fixed-mesh routing method. The circuit is partitioned into subblocks called Mesh-Routing Regions (MRs) in which clock skew is suppressed below a constant by mesh routing. Then the net from the clock source to each MR is routed as a balanced-tree. In using the technique to design an MPEG2-encoder LSI, a skew of 210 ps was achieved

Keywords

circuit layout CAD; digital integrated circuits; integrated circuit layout; network routing; timing circuits; MPEG2-encoder LSI design; balanced-mesh clock routing technique; balanced-tree configuration; circuit partitioning; clock skew suppression; mesh-routing regions; Classification tree analysis; Clocks; Combinational circuits; Delay effects; Integrated circuit interconnections; Laboratories; Large scale integration; Power dissipation; Routing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

European Design and Test Conference, 1996. ED&TC 96. Proceedings

Conference_Location

Paris

ISSN

1066-1409

Print_ISBN

0-8186-7424-5

Type

conf

DOI

10.1109/EDTC.1996.494155

Filename

494155

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3439091