Title :
A balanced-mesh clock routing technique using circuit partitioning
Author :
Sat, Hidenori ; Onozawa, Akira ; Matsuda, Hiroaki
Author_Institution :
NTT LSI Labs., Kanagawa, Japan
Abstract :
A clock routing technique using a balanced-mesh routing is proposed, which incorporates the advantages of both the well-known balanced-tree and fixed-mesh routing method. The circuit is partitioned into subblocks called Mesh-Routing Regions (MRs) in which clock skew is suppressed below a constant by mesh routing. Then the net from the clock source to each MR is routed as a balanced-tree. In using the technique to design an MPEG2-encoder LSI, a skew of 210 ps was achieved
Keywords :
circuit layout CAD; digital integrated circuits; integrated circuit layout; network routing; timing circuits; MPEG2-encoder LSI design; balanced-mesh clock routing technique; balanced-tree configuration; circuit partitioning; clock skew suppression; mesh-routing regions; Classification tree analysis; Clocks; Combinational circuits; Delay effects; Integrated circuit interconnections; Laboratories; Large scale integration; Power dissipation; Routing; Very large scale integration;
Conference_Titel :
European Design and Test Conference, 1996. ED&TC 96. Proceedings
Conference_Location :
Paris
Print_ISBN :
0-8186-7424-5
DOI :
10.1109/EDTC.1996.494155
