Title :
Defect based testing with a new ISB current strategy
Author_Institution :
Intel Israel (74) Ltd, Haifa, Israel
fDate :
30 March-4 April 2003
Abstract :
It is shown that in deep-sub-micron CMOS products, burn-in (BI) conditions can cause degradation of outgoing material because the electrical characterization of such material gives electrical signatures that correspond to integrated defect mechanisms. Sampling BI, with BI time adapted to reliability risk, is the first step to BI elimination. Standby current versus Vcc voltage is shown to be a good way for unit separation and reliability risk estimation.
Keywords :
CMOS integrated circuits; electric current measurement; failure analysis; integrated circuit reliability; integrated circuit testing; leakage currents; CMOS ULSI circuits; ISB current strategy; burn-in conditions; deep-sub-micron CMOS products; defect based testing; electrical characterization; electrical signatures; failure rate; integrated defect mechanisms; leakage current; reliability risk estimation; sampling BI; standby current; Bismuth; CMOS process; Circuit testing; Current measurement; Degradation; Integrated circuit reliability; Low voltage; Packaging; Sampling methods; Ultra large scale integration;
Conference_Titel :
Reliability Physics Symposium Proceedings, 2003. 41st Annual. 2003 IEEE International
Print_ISBN :
0-7803-7649-8
DOI :
10.1109/RELPHY.2003.1197825
