Pipelined modified Booth multiplication

Author

Wu, Angus ; Tang, K.C. ; Ng, C.K.

Author_Institution

Dept. of Electron. Eng., City Univ. of Hong Kong, Hong Kong

Volume

3

fYear

1998

fDate

1998

Firstpage

51

Abstract

A pipelined modified Booth multiplication is proposed to enhance the power performance ratio of 2´s complement multiplication. The system architecture of the proposed scheme is catered for VLSI implementation. It is designed with the merit of low power consumption achieved by reducing the number of adders required. Only half of the adders are required compared with the traditional pipelined multiplier

Keywords

VLSI; adders; carry logic; digital signal processing chips; low-power electronics; multiplying circuits; pipeline arithmetic; 2´s complement multiplication; VLSI implementation; fast parallel multiplication; low power consumption; low power design; partial product generation scheme; pipelined modified Booth multiplication; pipelined multiplier; power performance ratio; reduced number of adders; system architecture; Design engineering; Digital signal processing; Electronic design automation and methodology; Energy consumption; Impedance; Pipeline processing; Power engineering and energy; Throughput; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 1998 IEEE International Conference on

Conference_Location

Lisboa

Print_ISBN

0-7803-5008-1

Type

conf

DOI

10.1109/ICECS.1998.813934

Filename

813934