Title :
Time and voltage dependence of degradation and recovery under pulsed negative bias temperature stress
Author :
Usui, Hiroki ; Kanno, Michihiro ; Morikawa, Takafumi
Author_Institution :
S&S Archit. Center, Sony Corp., Tokyo, Japan
fDate :
30 March-4 April 2003
Abstract :
In order to determine the impact of the reliability of deep submicron LSIs with Negative Bias Temperature Instability (NBTI) induced P-channel MOS degradation, we studied P-MOS degradation phenomena using pulsed negative bias temperature (NBT) stress. P-MOS transistor drive current (IDS) degradation (ΔIDS) increased due to NBTI phenomena during the first stage of pulsed NBT stress of Vg, and ΔIDS decreased during the second stage of zero bias between gate and substrate. We studied the time dependence of ΔIDS and stress-voltage dependence during the cycle of the pulsed NBT stress. A degradation model is proposed.
Keywords :
CMOS logic circuits; MOSFET; integrated circuit reliability; recovery; semiconductor device reliability; 90 nm; 90 nm node CMOS technology; AC stress; NBTI; P-MOS degradation phenomena; P-MOS transistor drive current degradation; P-channel MOS degradation; deep submicron LSI reliability; degradation; degradation model; logic circuit design; negative bias temperature instability; p-MOSFET; pulsed NBT stress; pulsed negative bias temperature stress; recovery; stress voltage dependence; time dependence; Acquired immune deficiency syndrome; Degradation; Intrusion detection; MOSFET circuits; Negative bias temperature instability; Oxidation; Pulse circuits; Stress; Temperature dependence; Voltage;
Conference_Titel :
Reliability Physics Symposium Proceedings, 2003. 41st Annual. 2003 IEEE International
Print_ISBN :
0-7803-7649-8
DOI :
10.1109/RELPHY.2003.1197830
