Architectural study for an integrated fixed and floating-point VLSI-ASIC processor

The architecture of a single-chip processor with integrated fixed and floating-point execution units is presented. A single-chip implementation is enabled by current ASIC (application-specific integrated circuit) technology offering well in excess of 50000 gates per chip and delays on the order of 600 ps per gate. The basic principles of RISC (reduced-instruction-set-computer) architecture are used, and a fast floating-point processor is included as an integral part of the chip. The architecture is intended to make the processor attractive for a wide range of scientific computing when it is implemented as part of a special-purpose machine. The architecture takes advantage of the high level of integration and low power assumption of CMOS technology. The integration of the execution units and an efficient interunit communication protocol avoid off-chip delay penalties