DocumentCode
3439323
Title
A Single Poly CMOS Process Evaluation for Floating Gate Applications
Author
Badila, Marian ; Dunca, Tudor ; Cosmin, Peter
Author_Institution
Catalyst Semicond. Inc., Santa Clara, CA
Volume
2
fYear
2007
fDate
Oct. 15 2007-Sept. 17 2007
Firstpage
407
Lastpage
410
Abstract
The paper presents the experimental investigations made in order to introduce the floating gate tunability of analog circuit blocks combined with small memory EEPROM area for coded digital functions into a standard CMOS process.
Keywords
CMOS integrated circuits; EPROM; logic gates; analog circuit; coded digital functions; floating gate applications; single poly CMOS process; small memory EEPROM; standard CMOS process; CMOS process; CMOS technology; Capacitance; Capacitors; Circuits; Diodes; Double-gate FETs; EPROM; Nonvolatile memory; Tunneling;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Conference, 2007. CAS 2007. International
Conference_Location
Sinaia
ISSN
1545-827X
Print_ISBN
978-1-4244-0847-4
Type
conf
DOI
10.1109/SMICND.2007.4519745
Filename
4519745
Link To Document