A constant-geometry semisystolic architecture for the fast Hartley transform

Author

Zapata, E.L. ; Arguello, Francisco ; Bruguera, J.D.

Author_Institution

Dept. of Electron., Santiago Univ., Spain

fYear

1991

fDate

13-16 May 1991

Firstpage

238

Lastpage

242

Abstract

A parallel architecture is presented for the calculation of the fast Hartley transform (FHT) radix 2 which is adequate for its implementation in VLSI technology. A constant geometry (frequency decimation) algorithm for computing the FHT has been developed. The circuit proposed is characterized by its modular design and its interconnection regularity. It can be considered as semisystolic. It permits the computation of arbitrarily sized FHTs as a consequence of data recirculation over the processing units in all the stages of the transform. Each calculation stage requires N/4Q cycles, where N and Q are the length of the input real sequence and the number of processors respectively. The system calculates the FHT in log₂ N stages; therefore, the total calculation time is (N log₂ N)/4Q cycles

Keywords

VLSI; geometry; parallel architectures; systolic arrays; transforms; VLSI technology; constant-geometry semisystolic architecture; data recirculation; fast Hartley transform; frequency decimation; interconnection regularity; modular design; parallel architecture; total calculation time; Computational geometry; Contracts; Discrete Fourier transforms; Discrete transforms; Fast Fourier transforms; Frequency conversion; Integrated circuit interconnections; Parallel architectures; Physics; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

CompEuro '91. Advanced Computer Technology, Reliable Systems and Applications. 5th Annual European Computer Conference. Proceedings.

Conference_Location

Bologna

Print_ISBN

0-8186-2141-9

Type

conf

DOI

10.1109/CMPEUR.1991.257389

Filename

257389