Title :
1.5A DDR2 Termination Regulator
Author :
Stanescu, Cornel ; Aungurencei, Gabriel ; Franc, Fabien ; Voicu, Gelu
Author_Institution :
Catalyst Semicond. Romania S.R.L., Bucharest
fDate :
Oct. 15 2007-Sept. 17 2007
Abstract :
The paper presents a 1.5 A DDR2 termination regulator built in a 0.5 mum vanilla CMOS process. Theoretical considerations concerning the original chosen architecture are included. Simulations and experimental results indicate a fast load transient response at full plusmn1.5 A load.
Keywords :
CMOS memory circuits; transient response; voltage regulators; DDR2 termination regulator; current 1.5 A; double-data-rate memory; fast load transient response; size 0.5 mum; vanilla CMOS process; CMOS process; Circuit simulation; Diodes; Open loop systems; Pins; Power generation; Regulators; Resistors; Transient response; Voltage control;
Conference_Titel :
Semiconductor Conference, 2007. CAS 2007. International
Conference_Location :
Sinaia
Print_ISBN :
978-1-4244-0847-4
DOI :
10.1109/SMICND.2007.4519753
