Alternative strategies for applying min-cut to VLSI placement

The author describes the Silicon Convertor, 2 Dimension system (SC2D), which is an automatic layout synthesis system that accepts hierarchical circuit designs and produces detailed transistor-level layouts. It is suited to high-performance, full-custom chips, and offers a range of area/performance tradeoffs not available in conventional standard cell or gate-array techniques. The two-step approach is based on min-cut techniques combined with a placement evaluation function. The first step is optional: if higher-level hierarchy information is available, it can be utilized to group cells into clusters, and these clusters form the basis for a two-dimensional min-cut placement. In the second step, the clusters are dissolved and the cells internal to them placed using a stochastic two-dimensional min-cut placement technique that attempts to minimize a cost function. Finally, the logic cells are dissolved into their constituent transistors and the design proceeds with detailed placement and routing