A global chip test implementation including built-in self-test

The authors describe a systematic global test strategy and its implementation into a CMOS VLSI chip. Features include built-in self-test (BIST), embedded scan path, and boundary scan path for chip and board testability and diagnostics. The BIST implementation was derived from the sliding parity response compaction scheme and the boundary scan scheme was developed following the Joint Test Action Group Standard. The BIST method allows a systematic self-test design in a cell-based IC design methodology with a very high fault coverage in a very short test time. Critical parameters such as fault coverage, area overhead, performance degradation, and testing time are also reported