1.5 V CMOS bootstrapped dynamic logic circuit techniques (BDLCT) suitable for low-voltage deep-submicron CMOS VLSI for implementing 482 MHz digital quadrature modulator and adder

Author

Lou, J.H. ; Kuo, J.B.

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Volume

3

fYear

1998

fDate

1998

Firstpage

171

Abstract

This paper reports 1.5 V CMOS bootstrapped dynamic logic circuit techniques (BDLCT) suitable for low-voltage deep-submicron CMOS VLSI. Using BDLCT, the maximum operating frequency of a digital quadrature modulator is 482 MHz at 5 V and 68 MHz at 1.5 V. Compared to the circuit without BDLCT, the 12-bit delay time of a 16-bit adder with BDLCT is improved by 56% at 1.5 V

Keywords

CMOS logic circuits; adders; bootstrap circuits; carry logic; delays; integrated circuit design; logic design; low-power electronics; modulators; quadrature amplitude modulation; 0.5 mum; 1.5 V; 12-bit delay time; 16 bit; 16-bit adder; 482 MHz; 5 V; 68 MHz; CMOS bootstrapped dynamic logic circuit techniques; Manchester carry look-ahead circuit; digital quadrature modulator; low-voltage deep-submicron CMOS VLSI; maximum operating frequency; Adders; CMOS digital integrated circuits; CMOS logic circuits; CMOS technology; Delay effects; Digital modulation; Frequency; Logic circuits; Low voltage; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits and Systems, 1998 IEEE International Conference on

Conference_Location

Lisboa

Print_ISBN

0-7803-5008-1

Type

conf

DOI

10.1109/ICECS.1998.813960

Filename

813960