Title :
Asynchronous logic in bit-serial arithmetic
Author :
Povazanec, J. ; Choy, C.S. ; Chan, C.F.
Author_Institution :
Dept. of Electron. Eng., Chinese Univ. of Hong Kong, Shatin, Hong Kong
Abstract :
This article is an asynchronous approach to bit-serial processing. A new asynchronous cell (DCVSL like) was designed containing simplified “complete” signal generation as part of a dynamic handshake circuitry. The problem of data feedback has been addressed and its solution in a modified handshake protocol and local memory inclusion is given. Basic arithmetic components are demonstrated and a larger system is used as an example of this new cost effective technique
Keywords :
CMOS logic circuits; asynchronous circuits; digital arithmetic; integrated circuit design; logic design; parallel architectures; CMOS design; DCVSL like asynchronous cell; asynchronous logic; bit-serial arithmetic; bit-serial processing; complete signal generation; cost effective technique; data feedback; dynamic handshake circuitry; local memory inclusion; modified handshake protocol; Adders; Arithmetic; Asynchronous circuits; Books; Buildings; Costs; Digital signal processing; Feedback; Logic; Silicon;
Conference_Titel :
Electronics, Circuits and Systems, 1998 IEEE International Conference on
Conference_Location :
Lisboa
Print_ISBN :
0-7803-5008-1
DOI :
10.1109/ICECS.1998.813961
